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◆ csr_clear_bits
#define csr_clear_bits |
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reg, |
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bits |
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| asm volatile("csrc " #reg ", %0" : : "r"(bits)) |
◆ csr_read
Value: ({ \
usize val; \
asm
volatile(
"csrr %0, " #
reg :
"=r"(val)); \
val; \
})
#define reg(reg)
Definition: plic.c:11
◆ CSR_SCAUSE_ECALL_U
#define CSR_SCAUSE_ECALL_U 8 |
◆ CSR_SCAUSE_EXT_INTR
#define CSR_SCAUSE_EXT_INTR 9 |
◆ CSR_SCAUSE_INTR
#define CSR_SCAUSE_INTR 0x8000000000000000 |
◆ CSR_SCAUSE_TIMER_INTR
#define CSR_SCAUSE_TIMER_INTR 5 |
◆ csr_set_bits
#define csr_set_bits |
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reg, |
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bits |
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) |
| asm volatile("csrs " #reg ", %0" : : "r"(bits)) |
◆ CSR_SIE_SEIE
#define CSR_SIE_SEIE 0x200 |
◆ CSR_SIE_STIE
#define CSR_SIE_STIE 0x20 |
◆ CSR_SSTATUS_SPIE
#define CSR_SSTATUS_SPIE 0x20 |
◆ CSR_SSTATUS_SPP
#define CSR_SSTATUS_SPP 0x100 |
◆ csr_write
#define csr_write |
( |
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reg, |
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val |
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) |
| asm volatile("csrw " #reg ", %0" : : "r"(val)) |